Multi stacked layer structure analysis (above 3 layer)
Customizations of H/W, S/W, and Communication functions
Max 12” foup-based load/unload
Pattern recognition for multi-layer on pattern wafer
Real-time measurement of Si wafer thickness at CMP or backside grinding
Non-contact and non-destructive measurement available
Original analytical algorithm for thickness measurement (patent granted)
Real-time measurement of Si wafer thickness
3 types of optional stage - Rθ, XY, RθXY
High precision and high speed measurement
Compatible with a spare unit of 300mm EFEM port
6F, 41, Seongnam-daero 925beon-gil, Bundang-gu, Seongnam-si, Gyeonggi-do, 13496, Republic of Korea
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